The present invention relates generally to semiconductor integrated circuits and, more particularly, to dynamic random access memory (DRAM) technology compatible non volatile memory cells.
With the increasing array density of successive generations of DRAM chips, the attractiveness of merging other functions onto the DRAM process chip also increases. However, any successful merged technology product must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing DRAM technology in order to provide added functions such as high speed logic, SRAM or EEPROM becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield. Thus, there is a need for a means of providing additional functions on a DRAM chip with little or no modification of the DRAM optimized process flow.
Among the desired additional functions, incorporating non volatile memory capability into a DRAM process flow is one area for which the differences between the separately optimized technologies is the greatest. Electronically erasable and reprogrammable read only memory (EEPROM) cells represent one form of non-volatile memory. EEPROM cells can be electrically programmed, erased, and reprogrammed. The typical EEPROM cell consists of a MOSFET with two stacked gates, a floating gate directly over the device channel and a control gate atop and capacitively coupled to it. Since the floating gate is electrically isolated, any charge stored on the floating gate is trapped. Storing sufficient negative charge on the floating gate will suppress the creation of an inversion channel between source and drain of the MOSFET. Thus, the presence or absence of charge on the floating gate represents two distinct data states. Or the level of change represents a plurality of data states.
Typically, EEPROM cells are selectively programmed by hot electron injection which places a negative charge on a floating gate during a write. The EEPROM cells are selectively erased by Fowler-Nordheim tunneling which removes the a charge from the floating gate. During a write, a high programming voltage is placed on the control gate. This forces an inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage (6 volts) while the source is grounded (0 volts), increasing the voltage drop between the drain and source. In the presence of the inversion region, the current between the drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the outside barrier and collect on the floating gate.
After the write is completed, the negative charge on the floating gate raises the cell""s threshold voltage (Vt) above the wordline logic 1 voltage. When a written cell""s wordline is brought to a logic 1 during a read, the MOSFET in the EEPROM cell will not turn on. Sense amps detect and amplify the cell current, and output a 0 for a written cell.
The floating gate can be erased by grounding the control gate and raising the source voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the source terminal of the transistor by tunneling through the insulating gate oxide. After the erase is completed, the lack of charge on the floating gate lowers the cell""s Vt below the wordline logic 1 voltage. Thus when an erased cell""s wordline is brought to a logic 1 during a read, the transistor will turn on and conduct more current than a written cell. Some EEPROM cells use Fowler-Nordheim tunneling for writes as well as erase.
The EEPROM cells can be selectively reprogrammed in the same manner as described above, since the Fowler-Nordheim tunneling process is nondestructive. The programming and erasure voltages which effect Fowler-Nordheim tunneling are higher than the voltages normally used in reading the memory. Thus the Fowler-Nordheim tunneling effect is negligible at the lower voltages used in reading the memory, allowing a EEPROM cell to maintain its programmed state for years if subjected only to normal read cycles.
The programming voltages required for EEPROM operation pose an additional problem to merging EEPROM and DRAM chip technologies. The EEPROM cell includes a capacitor plate which must be fabricated with a large enough area to retain a charge sufficient to withstand the effects of parasitic capacitances and noise due to circuit operation. The increased cell array density found on DRAM chips places significant constraints on the size of the EEPROM capacitor plate, Typically, smaller cell designs necessitate increasing programming voltages in order to retain required capacitance levels. Increasing the programming voltage, however, increases the power dissipation and future generations of EEPROM cells will require lower power dissipation.
Modem DRAM technologies are driven by market forces and technology limitations to converge upon a high degree of commonality in basic cell structure. For the DRAM technology generations from 4 Mbit through 1 Gbit, the cell technology has converged into two basic structural alternatives; trench capacitor and stacked capacitor. A method for utilizing a trench DRAM capacitor technology to provide a compatible EEPROM cell has been described in U.S. Pat. No. 5,598,367. A different approach is needed for stacked capacitors however.
Thus, there is a need for novel DRAM technology compatible non volatile memory cells. It is desirable that such DRAM technology compatible non volatile memory cells be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. It is further desirable that such DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
The above mentioned problems for merging other functions onto the DRAM chip as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention includes a compact non volatile memory cell structure formed using a stacked DRAM capacitor technology.
In one embodiment a non volatile memory cell structure is provided. The non volatile memory cell includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor.
In another embodiment, an array of non volatile memory cells is provided. The array of non volatile memory cells includes a number of non volatile memory cells. Each non volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. Each non volatile memory cell includes a stacked capacitor which has a bottom plate, a capacitor dielectric, and a top plate. The stacked capacitor is formed in a subsequent layer above the MOSFET and is separated from the MOSFET by an insulator layer. An electrical contact couples the bottom plate of the stacked capacitor to a gate of the MOSFET through the insulator layer. A wordline is coupled to the top plate of the stacked capacitor in the number of non volatile memory cells. A bit line is coupled to a drain region of the MOSFET in the number of non volatile memory cells. And, a sourceline is coupled to a source region of the MOSFET in the number of non volatile memory cells.
In another embodiment, a method for forming a non volatile memory cell on a DRAM chip is provided. The method includes forming a metal oxide semiconductor field effect transistor (MOSFET) in a substrate on the DRAM chip. The method includes forming a stacked capacitor above a gate of the MOSFET using a DRAM process. The stacked capacitor is separated from the MOSFET by an insulator layer. An electrical contact is formed using a DRAM process such that the electrical contact couples a bottom plate of the stacked capacitor to the gate of the MOSFET through the insulator layer.
In another embodiment, a method for operating a memory cell is provided. The method includes controlling a charge placed on a gate of a metal oxide semiconductor field effect transistor (MOSFET) and placed on a bottom plate of a stacked capacitor which is coupled to the gate by an electrical contact through an insulator layer. Controlling the charge placed on the gate and on the bottom plate regulates a threshold voltage (Vt) for the memory cell.
These and other embodiments, aspects, advantages; and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.